abstraction
    level, 7, 19
accuracy, 14
algorithm, 10, 66
aligned, 85
alignment, 86
analog-to-digital converter, 76
    implementation, 79
    pins, 76
    registers, 76
    sampling, 79
architecture, 10
attribute, 26

behavior, 9
block
    stateful, 94
    stateless, 94
board, 1
bootstrap, 23, 25, 42, 70
bus
    interface, 58
    master, 63
    port, 58
    signal, 57

callback, 44, 59, 60, 97, 101, 107
channel, 84, 90
chip, 1
circuit, 10
class, 26
clock, 37, 62
    prescaled, 78
code
    optimization, 8
configuration, 57
coverage, 52
    functional, 52
    hardware code, 52

data
    exchange, 103
    object, 26, 30
    type, 26, 34
divisor, 85
DLL, 99
double buffering, 88

elaboration, 25, 42, 57, 59, 70, 81, 102
emulation, see verification
execution, 40, 61

function, 8, 12
functional network, 8

gain block, 93
Gajski, 10
geometry, 9
granularity, 109

HDL, 7, 9
hierarchy, 18
Hiwave, 81, 90, 119

IC, 1, 5
IEEE, 15, 22, 23, 37, 57, 123, 124
initialization, 43, 60, 70, 97, 105
integral, 93
interface, 100
interoperability, 22
IP
    block, 5

library, 29, 96
logic, 10, 16
logical system architecture, 8

MathWorks, 73, 93
migration, 54
model
    abstraction, 9
    behavioral, 18
    boundary, 29, 43
    boundary class, 24, 26, 68
    bus functional, 19
    characteristics, 51
    class, 17
    dataflow graph, 20
    functional, 17
    integration, 75
    interface, 19, 60, 75
    interface behavior, 19
    manager, 5, 22, 23, 26, 41, 57, 59
    memory, 75
    mixed-level, 20
    performance, 19
    structural, 18
    vendor, 5, 22
Motorola, 4, 57, 73, 115
MSRS, 74

netlist, 53, 62, 67, 70
Nyquist frequency, 111

object, 26
    root, 28
Octopus, 57, 79
    classification, 64
OMI, 22, 67
    information model, 26, 27, 39, 68
Open Model Forum, 22
Open Model Interface, see OMI

parameter, 26, 31
peripheral, 21, 73, 74
    integrated, 74
polarity, 86
port, 26, 31, 57, 58, 100, 105
    digital, 79
    direction, 69
    non-atomic, 32
    update, 62
prescaler, 85, 89
processor, 21
production, 1
    cost, 1
    process, 1
    time, 1
propagation, 44
property, 26
pulse width modulator, 84
    implementation, 87
    pins, 85
    registers, 84

RASSP, 11
register map, 76, 85, 89
relationship, 26
    multiple, 28
    singular, 28
resolution
    data, 15, 65
    effective, 19
    functional, 15
    software programming, 16, 67
    structural, 16, 67
    temporal, 14
reuse, 57
RTL, 7, 8

S-function, 95, 96
sample time, 98
    continuous, 98
    discrete, 98
    inherited, 99
    variable, 98
scenario, 7
SDF, see standard delay format
signal, 61
    clock, 111
    technology, 58
    update, 110
signal generator, 93
silicon transistor, 1
simulation, 43, 59, 70, 94, 102
    cycle-based, 25, 37, 44
    event-driven, 25, 57
    performance, 80
    random pattern, 50
    speed, 57
    style, 25
simulator
    interface, 102
Simulink, 73, 75, 93, 119
standard delay format, 37, 69
Star12, 73, 100
structure, 9, 12
synchronization, 112
System-on-Chip, 1

taxonomy, 8, 10, 11, 17, 67
technical system architecture, 8
termination, 47, 70
test case, 83
timeline, 58
timing, 37, 69
    signal timing, 21
    step size, 108
    synchronization, 108
token, 57
topology, 19
transistor, 1
trigger, 76
type
    array, 35
    C, 27
    completely characterized, 30
    enumeration, 35
    incompletely characterized, 34
    primitive, 26

UML, 10

verification, 47
    coverage, see coverage
    dynamic, 50, 54
    emulation, 48, 49
    equivalence, 53
    formal, 49
    formal equivalence checking, 53
    integration, 55
    metrics, 52
    model checking, 49
    physical, 53
    prototyping, 48
    summary, 55
    theorem proving, 49
    virtual prototyping, 51
Verilog, 21, 23
VHDL, 9, 11, 21, 23
viewport, 26, 33, 43
    composite, 33
virtual component, 5, 22, 55, 57
VSIA, 6, 11, 48, 67
VSI Alliance, see VSIA

Y-chart, 9