Application Specific Integrated Circuit. As its full name implies, an ASIC is a custom microchip designed for a specific application. Of course, the chip doesn’t reinvent the wheel: ASIC design involves taking common functions from a library and integrating them onto a circuit. [CN01]

Field-Programmable Gate Array. Technique for a test-implementation of ICs or for production of very small series. The circuits are burnt into a matrix of transistors.

Hardware Description Language. A language used to describe hardware in a such a way that a layout can be generated from the description. It is the last step before the physical layout is created. Here all entities like memory cells are modeled. Very common HDLs today are Verilog and VHDL.

Integrated Circuit. A complete functionality encapsulated usually in a chip or integrated into a SoC.

In-Circuit Emulator. Technique for realizing a physical prototype by building a reconfigurable prototyping system.

Instruction Set Architecture. This is how the instruction set of a CPU does look like and how it works. It includes the list of instructions as well as their semantics and timings.

Ordinary Differential Equations. Differential equations arising from assembling circuit representations to simulation models.

Open Model Forum. Group "formed to solve the problem of logic model availability." [IEE99, p. iii]

Open Model Interface. Interface between models and simulators. Language independent. Specification in IEEE Std 1499.

Open Verilog International. Former group that developed standards for systems, semiconductor and design tools. Has joined the VHDL International in 2000 and founded Accellera. http://www.accellera.org/

Register Transfer Language. Register Transfer Language (RTL) is a concise way of specifying micro code instructions. Micro code is a level below assembly language, which is itself a level below high level languages like C and C++. So RTL can be viewed as the opcode.

Standard Delay Format. The Standard Delay Format is subject to become IEEE Std 1497, it was developed by a group named Open Verilog International which is now part of the Accellera group. Referring to the specification [Hor95], a SDF file "stores the timing data generated by EDA tools for use at any stage in the design process." This can include delays, timing checks, timing constraints, timing environments, incremental and absolute delays, conditional and unconditional module path delays, design- or instance-specific data, type- or library-specific data and scaling, environmental and technology parameters. http://www.eda.org/sdf/

System-on-Chip. multiple ICs integrated into one chip. Replaces former integration boards

Vector Change Dump. VCD is a file format used to save signals, analog and digital. It is specified in IEEE Std 1364-1995 ([IEE95, chapter 15]).