2.1.  Model Abstraction Levels

The design of a chip is not a straightforward procedure. No one starts, designing a chip, by running a CAD program and draw the layout of the circuits. Usually, the known thing is a set of functionality, which has to be covered by the system. The design team refines this set of functionality into a specification. Starting with the description of functionality, the specification refines to register level, timing aspects will occur, the specification will be translated to a register-transfer-language (RTL), a hardware description language (HDL) and at the end, there is the layout. Different levels of abstraction are used to design the system, from high-level abstraction to low level abstraction. Each level has its own intents of behavior it describes; let it be timing or data values, functions or structure. Each aspect has to be verified and tested, so each level must be accompanied with a simulation model of the whole system. A high level model allows to verify the requirements to the system, evaluate different architectural aspects and test the usability of existing components in respect of the system’s needs.

  2.1.1  A basic abstraction model
  2.1.2  Gajski-Kuhn chart
  2.1.3  The VSIA approach
   2.1.3.1  Taxonomy Definition
   2.1.3.2  Model Classes
   2.1.3.3  Special Models