Joachim Schlosser: Development and Verification of fast C/C++ Simulation Models for the Star12 Microcontroller
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2.3.4. VC Verification versus Integration
Verification
VC verification utilizes no own techniques but covers both, intent verification and
equivalence checking. Generally a higher level of abstraction allows higher performance in
testing. With RTL being the highest level of abstraction, many tools like model
and equivalence checkers support, it is the typical level for intent verification.
Equivalence checking is usually done at the lowest level of abstraction like net
lists.
Like the VC verification, integration verification is rather an appliance than a technique.
The difference between model checking and integration verification is the different view:
The whole SoC has to work. In most cases gray-box models will suffice as they accurately
model the VCs interfaces.